A place-aware redundancy methodology for multi-cell upsets mitigation in NoC-Reference-Cited by-同舟云学术

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A place-aware redundancy methodology for multi-cell upsets mitigation in NoC

Published:2018 Issue:21 Volume:15 Page:20180777-20180777
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Jiao Jiajia¹,Wang JiaBin¹,Han Dezhi¹

Affiliation:

1. College of Information Engineering, Shanghai Maritime University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/15/21/15_15.20180777/_pdf

Reference10 articles.

1. [1] R. C. Baumann: “Radiation-induced soft errors in advanced semiconductor technologies,” IEEE Trans. Device Mater. Rel. 5 (2005) 305 (DOI: 10.1109/TDMR.2005.853449).

2. [2] K. Constantinides, et al.: “Bulletproof: A defect-tolerant CMP switch architecture,” High-Performance Computer Architecture (2006) 5 (DOI: 10.1109/HPCA.2006.1598108).

3. [3] F. T. Bortolon, et al.: “Exploring the impact of soft errors on NoC-based multiprocessor systems,” Circuits and Systems (ISCAS) (2018) 1 (DOI: 10.1109/ISCAS.2018.8351391).

4. [4] D. Alexandrescu: “A comprehensive soft error analysis methodology for SoCs/ASICs memory instances,” On-Line Testing Symposium (2011) 175 (DOI: 10.1109/IOLTS.2011.5993833).

5. [5] J. Jiao, et al.: “Accelerated assessment of fine-grain AVF in NoC using a multi-cell upsets considered fault injection,” Microelectron. Reliab. 54 (2014) 2629 (DOI: 10.1016/j.microrel.2014.06.008).

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