Effectiveness of the layout approach in mitigating single event transients in 65-nm bulk CMOS process
Author:
Affiliation:
1. School of Microelectronics, Xidian University
2. Science and Technology on Analog Integrated Circuit Laboratory
3. School of Electrical and Electronic Engineering, Chongqing University of Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/15/13/15_15.20180540/_pdf
Reference11 articles.
1. [1] M. J. Gadlage, et al.: “Increased single-event transient pulsewidths in a 90-nm bulk CMOS technology operating at elevated temperatures,” IEEE Trans. Device Mater. Rel. 10 (2010) 157 (DOI: 10.1109/TDMR.2009.2036719).
2. [2] T. Li, et al.: “A novel SEU hardened SRAM bit-cell design,” IEICE Electron. Express 14 (2017) 20170413 (DOI: 10.1587/elex.14.20170413).
3. [3] P. Li, et al.: “Effect of charge sharing on SEU sensitive area of 40-nm 6T SRAM cells,” IEICE Electron. Express 11 (2014) 20140051 (DOI: 10.1587/elex.11.20140051).
4. [4] H. Xu and Y. Zeng: “A novel layout placement structure to mitigate the multi-bit-upset in 6T-SRAM cell,” IEICE Electron. Express 11 (2014) 20140396 (DOI: 10.1587/elex.11.20140396).
5. [5] J. Guo, et al.: “Novel radiation-hardened-by-design (RHBD) 12T memory cell for aerospace applications in nanoscale CMOS technology,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25 (2017) 1593 (DOI: 10.1109/TVLSI.2016.2645282).
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