Phase difference analysis technique for parametric faults BIST in CMOS analog circuits
Author:
Affiliation:
1. VLSI Design and Automotion Research Laboratory, Kochi University of Technology
2. Center of Excellence in Intelligent System Integration, Thai-Nichi Institute of Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/15/9/15_15.20180175/_pdf
Reference14 articles.
1. [1] J. W. Jeong, et al.: “Robust amplitude measurement for RF BIST applications,” IEEE European Test Symposium (ETS) (2015) 1 (DOI: 10.1109/ETS.2015.7138762).
2. [2] W. San-Um and T. Masayoshi: “Impulse signal generation and measurement technique for cost-effective built-in self test in analog mixed-signal systems,” IEEE Int. Midwest Symp. Circuits and Systems (2009) 1195 (DOI: 10.1109/MWSCAS.2009.5235949).
3. [3] G. Hu, et al.: “Oscillation test strategy for analog filters by monitoring output voltage and supply current,” Tsinghua Sci. Technol. 12 (2007) 78 (DOI: 10.1016/S1007-0214(07)70088-3).
4. [4] K. Kim, et al.: “A low-cost BIST based on histogram testing for analog to digital converters,” IEICE Trans. Electron. E91-C (2008) 670 (DOI: 10.1093/ietele/e91-c.4.670).
5. [5] G. Renaud, et al.: “Design of an on-chip stepwise ramp generator for ADC static BIST applications,” IEEE Int. Mixed-Signals Testing Workshop (IMSTW) (2015) 1 (DOI: 10.1109/IMS3TW.2015.7177876).
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