A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction

Author:

Nguyen Khai-Duy1,Kiet Dang Tuan1,Hoang Trong-Thuc1,Quynh Nguyen Quang Nhu2,Tran Xuan-Tu3,Pham Cong-Kha1

Affiliation:

1. University of Electro-Communications (UEC)

2. The University of Danang, University of Science and Technology (DUT)

3. The Information Technology Institute (VNU-ITI)

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference32 articles.

1. [1] A. Waterman, et al.: “The RISC-V instruction set manual, volume I: user-level ISA, version 2.0,” UC Berkeley UCB/EECS-2014-54 (2014) https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf.

2. [2] K. Asanović, et al.: “The rocket chip generator,” UC Berkeley UCB/EECS-2016-17 (2016) https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.pdf.

3. [3] SiFive, Inc.: “SiFive E31 manual,” (2019) https://sifive.cdn.prismic.io/sifive%2Fc89f6e5a-cf9e-44c3-a3db-04420702dcc1_sifive+e31+manual+v19.08.pdf.

4. [4] SiFive, Inc.: “SiFive E54-MC Manual,” (2019) https://sifive.cdn.prismic.io/sifive/86e05812-e9cd-4553-bfef-c7e715088055_sifive_coreip_U54MC_AXI4_rtl_v19_08p2p0_release_manual.pdf.

5. [5] M. Johns, et al.: “A minimal RISC-V vector processor for embedded systems,” Forum for Spec. and Design Lang. (2020) 20085586 (DOI: 10.1109/FDL50818.2020.9232940).

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