An implementation of fast polar codes decoder with reducing internal memory and supporting flexible code rate
Author:
Affiliation:
1. University of Chinese Academy of Sciences
2. University of Posts and Telecommunications
3. Institute of Microelectronics of Chinese Academy of Sciences
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/19/2/19_18.20210503/_pdf
Reference30 articles.
1. [1] E. Arikan: “Channel polarization: a method for constructing capacity achieving codes for symmetric binary-input memoryless channels,” IEEE Trans. Inf. Theory 55 (2009) 3051 (DOI: 10.1109/TIT.2009.2021379).
2. [2] C. Leroux, et al.: “A semi-parallel successive-cancellation decoder for polar codes,” IEEE Trans. Signal Process. 61 (2013) 289 (DOI: 10.1109/TSP.2012.2223693).
3. [3] A.J. Raymond and W.J. Gross: “A scalable successive-cancellation decoder for polar codes,” IEEE Trans. Signal Process. 62 (2014) 5339 (DOI: 10.1109/TSP.2014.2347262).
4. [4] B. Yuan and K.K. Parhi: “Low-latency successive-cancellation polar decoder architectures using 2-bit decoding,” IEEE Trans. Circuits Syst. I, Reg. Papers 61 (2014) 1241 (DOI: 10.1109/TCSI.2013.2283779).
5. [5] R. Shrestha and A. Sahoo: “High-speed and hardware-efficient successive cancellation polar-decoder,” IEEE Trans. Circuits Syst. II, Exp. Briefs 66 (2019) 1144 (DOI: 10.1007/s11265-018-1413-4).
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