A 30Gbps 1.25pJ/b CMOS receiver analog front-end with low supply voltage

Author:

Zhou Gaolei1,Mao Luhong1,Xie Sheng2,Min Chuang2

Affiliation:

1. Dept. of Electrical and Information Engineering, Tianjin University

2. Dept. of Microelectronics, Tianjin University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference32 articles.

1. [1] A. Awny, et al.: “A 40Gb/s monolithically integrated linear photonic receiver in a 0.25µm BiCMOS SiGe:C technology,” IEEE Microw. Wireless Compon. Lett. 25 (2015) (DOI: 10.1109/lmwc.2015.2430615).

2. [2] R.Y. Chen and Z.-Y. Yang: “CMOS transimpedance amplifier for gigabit-per-second optical wireless communications,” IEEE Trans. Circuits Syst. II, Exp. Briefs 63 (2016) (DOI: 10.1109/tcsii.2015.2505264).

3. [3] P.-C. Chiang, et al.: “4×25Gb/s transceiver with optical front-end for 100GbE system in 65Nm CMOS technology,” IEEE J. Solid-State Circuits 50 (2015) (DOI: 10.1109/jssc.2014.2365700).

4. [4] C. Li and S. Palermo: “A low-power 26-Ghz transformer-based regulated cascode SiGe BiCMOS transimpedance amplifier,” IEEE J. Solid-State Circuits 48 (2013) (DOI: 10.1109/jssc.2013.2245059).

5. [5] C.-F. Liao and S.-I. Liu: “40Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90Nm CMOS,” IEEE J. Solid-State Circuits 43 (2008) (DOI: 10.1109/jssc.2007.916626).

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