Unit cell mismatch scrambling method for high-resolution unary DAC based on virtual 3D layout-Reference-Cited by-同舟云学术

Unit cell mismatch scrambling method for high-resolution unary DAC based on virtual 3D layout

Published:2022-12-25 Issue:24 Volume:19 Page:20220430-20220430
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Yao Dan¹,Bai Xuanyan¹,Katayama Shogo¹,Kuwana Anna¹,Kawauchi Kazuyuki¹,Kobayashi Haruo¹,Hirai Kouji²,Suzuki Akira²,Yamada Satoshi²,Kato Tomoyuki²,Kitakoga Ritsuko²,Shimamura Takeshi²,Adhikari Gopal²,Ono Nobuto²,Miura Kazuhiro²,Yamaguchi Shigeya²

Affiliation:

1. Division of Electronics and Informatics, Gunma University

2. Jedat Inc.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/19/24/19_19.20220430/_pdf

Reference30 articles.

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3. [3] I. Galton: “Why dynamic-element-matching DACs work,” IEEE Trans. Circuits Syst. II, Exp. Briefs 57 (2010) 69 (DOI: 10.1109/tcsii.2010.2042131).

4. [4] M. Kilic, et al.: “A row-column accessed dynamic element matching DAC architecture for SAR ADCs,” IEEE Nordic Circuits and Systems Conference and International Symposium of System-on-Chip (2018) (DOI: 10.1109/norchip.2018.8573513).

5. [5] T. Miki, et al.: “An 80-MHz 8-bit CMOS D/A converter,” IEEE J. Solid-State Circuits 21 (1986) 983 (DOI: 10.1109/jssc.1986.1052639).