A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router
Author:
Affiliation:
1. School of Information Technology, Guangdong Industry Polytechnic
2. State Key Laboratory of Wide Bandgap Semiconductor Technology Disciplines, Xidian University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/20/2/20_19.20220078/_pdf
Reference32 articles.
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3. [3] Y.-H. Kao and H.J. Chao: “Design of a bufferless photonic clos network-on-chip architecture,” IEEE Trans. Comput. 63 (2014) 764 (DOI: 10.1109/TC.2012.250).
4. [4] G. Michelogiannakis and W.J. Dally: “Elastic buffer flow control for on-chip networks,” IEEE Trans. Comput. 62 (2013) 295 (DOI: 10.1109/TC.2011.237).
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