Optimal horizon size for unbiased finite memory digital phase-locked loop
Author:
Affiliation:
1. School of Electrical Engineering, Korea University
2. Department of Electrical Engineering, Wonkwang University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/14/3/14_14.20161184/_pdf
Reference24 articles.
1. [1] W. C. Lindsey and C. M. Chie: “A survey of digital phase-locked loops,” Proc. IEEE 69 (1981) 410 (DOI: 10.1109/PROC.1981.11986).
2. [2] P. Heydari: “Analysis of the PLL jitter due to power/ground and substrate noise,” IEEE Trans. Circuits Syst. I, Reg. Papers 51 (2004) 2404 (DOI: 10.1109/TCSI.2004.838240).
3. [3] C. H. Leeet al.: “A supply noise insensitive PLL design through PWL behavioral modeling and simulation,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 48 (2001) 1137 (DOI: 10.1109/82.988939).
4. [4] R. R. Manikandan and B. Amrutur: “Experimental study on substrate noise effect of a pulsed clocking scheme on PLL performance,” IEEE Trans. Circuits Syst. II, Exp. Briefs 60 (2013) 852 (DOI: 10.1109/TCSII.2013.2281942).
5. [5] A. Patapoutian: “On phase-locked loops and Kalman filters,” IEEE Trans. Commun. 47 (1999) 670 (DOI: 10.1109/26.768758).
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Memory parameterized FIR filtering for digital phase-locked loop;IEICE Electronics Express;2019
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