Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression-Reference-Cited by-同舟云学术

Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression

Published:2017 Issue:11 Volume:14 Page:20170399-20170399
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Lee Sang Muk¹,Jang Ji Hoon¹,Oh Jung Hwan¹,Kim Ji Kwang¹,Lee Seung Eun¹

Affiliation:

1. Dept. of Electronic Engineering, Seoul National University of Science and Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/14/11/14_14.20170399/_pdf

Reference11 articles.

1. [1] A. M. Caulfield, et al.: “A cloud-scale acceleration architecture,” IEEE/ACM International Symposium on Microarchitecture (2016) (DOI: 10.1109/MICRO.2016.7783710).

2. [2] M. Staveley, “Applications that scale using GPU compute,” AzureCon (2015).

3. [3] J. Ouyang, et al.: “SDA: Software-defined accelerator for large-scale DNN systems,” HotChips (2014) (DOI: 10.1109/HOTCHIPS.2014.7478821).

4. [4] AHA378 (2015) http://www.aha.com/data-compression/.

5. [5] S. M. Lee, et al.: “A hardware scheduler for multicore block cipher processor,” PDP (2016) (DOI: 10.1109/PDP.2016.59).

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