A novel complementary push-push frequency doubler with negative resistor conversion gain enhancement

Author:

Liu Yang1,Li Zhiqun1,Gao Hao12,Li Qin1,Wang Zhigong1

Affiliation:

1. Institute of RF-& OE-ICs, Southeast University

2. Eindhoven University of Technology, Delft University of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference10 articles.

1. [1] M. Ferndahl, et al.: “40 and 60 GHz frequency doublers in 90-nm CMOS,” IEEE MTT-S Int. Dig. 1 (2004) 179 (DOI: 10.1109/MWSYM.2004.1335837).

2. [2] J. Chen, et al.: “A 50–70 GHz frequency doubler in 90 nm CMOS,” IEEE MTT-S Int. Microw. Workshop Series on Millim. Wave Wirel. Tech. and Appl. (IMWS) (2012) 1 (DOI: 10.1109/IMWS2.2012.6338190).

3. [3] K. Y. Lin, et al.: “A 14–23 GHz CMOS MMIC distributed doubler with a 22-dB fundamental rejection,” IEEE MTT-S Int. Microw. Symp. Dig. (2008) 1477 (DOI: 10.1109/MWSYM.2008.4633059).

4. [4] K. Y. Linet al.: “A K-band CMOS distributed doubler with current-reuse technique,” IEEE Microw. Wireless Compon. Lett. 19 (2009) 308 (DOI: 10.1109/LMWC.2009.2017598).

5. [5] Y. A. Laiet al.: “Compact doubler with simple harmonic suppression and gain-compensation functions,” IEEE Microw. Wireless Compon. Lett. 21 (2011) 371 (DOI: 10.1109/LMWC.2011.2152383).

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