A single event transient detector in SRAM-based FPGAs
Author:
Affiliation:
1. School of Electronic Science and Applied Physics, Hefei University of Technology
2. School of Mathematics, Hefei University of Technology
3. School of Computer Science and Technology, Anhui University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/14/12/14_14.20170210/_pdf
Reference11 articles.
1. [1] W. Xuet al.: “In-place FPGA retiming for mitigation of variational single-event transient faults,” IEEE Trans. Circuits Syst. I, Reg. Papers 58 (2011) 1372 (DOI: 10.1109/TCSI.2010.2094370).
2. [2] M. Darvishiet al.: “Circuit level modeling of extra combinational delays in SRAM-based FPGAs due to transient ionizing radiation,” IEEE Trans. Nucl. Sci. 61 (2014) 3535 (DOI: 10.1109/TNS.2014.2369424).
3. [3] S. Rezguiet al.: “SET characterization and mitigation in 65-nm CMOS test structures,” IEEE Trans. Nucl. Sci. 59 (2012) 851 (DOI: 10.1109/TNS.2012.2196768).
4. [4] V. Ferlet-Cavroiset al.: “Investigation of the propagation induced pulse broadening (PIPB) effect on single event transients in SOI and bulk inverter chains,” IEEE Trans. Nucl. Sci. 55 (2008) 2842 (DOI: 10.1109/TNS.2008.2007724).
5. [5] L. Sterponeet al.: “An analytical model of the propagation induced pulse broadening (PIPB) effects on single event transient in flash-based FPGAs,” IEEE Trans. Nucl. Sci. 58 (2011) 2333 (DOI: 10.1109/TNS.2011.2161886).
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Experimental verification of the effectiveness of a new circuit to mitigate single event upsets in a Xilinx Artix-7 field programmable gate array;Microprocessors and Microsystems;2020-11
2. Characterization and Mitigation of Single-Event Transients in Xilinx 45-nm SRAM-Based FPGA;IEEE Transactions on Nuclear Science;2019-06
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