Extended coset decoding scheme for multi-bit asymmetric errors in non-volatile memories-Reference-Cited by-同舟云学术

Extended coset decoding scheme for multi-bit asymmetric errors in non-volatile memories

Published:2017 Issue:21 Volume:14 Page:20170919-20170919
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Liu Liwen¹,Zhuang Yiqi¹,Zhang Li¹,Xin Xiang¹

Affiliation:

1. School of Microelectronics, Xidian University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/14/21/14_14.20170919/_pdf

Reference26 articles.

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3. [3] M. White, et al.: “A study of scaling effects on dram reliability,” IEEE Proc.-Annual Reliability and Maintainability Symposium (RAMS) (2011) 6 (DOI: 10.1109/RAMS.2011.5754522).

4. [4] X. Donget al.: “NVSim: A circuit-level performance, energy, and area model for emerging nonvol-atile memory,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 31 (2012) 994 (DOI: 10.1109/TCAD.2012.2185930).

5. [5] C. Chappertet al.: “The emergence of spin electronics in data storage,” Nat. Mater. 6 (2007) 813 (DOI: 10.1038/nmat2024).

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