Low-latency and memory-efficient SDF IFFT processor design for 3GPP LTE-Reference-Cited by-同舟云学术

Low-latency and memory-efficient SDF IFFT processor design for 3GPP LTE

Published:2017 Issue:12 Volume:14 Page:20170395-20170395
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Kim Yeon-Jin¹,Jang In-Gul²,Cho Kyung-Ju³,Chung Jin-Gyun¹

Affiliation:

1. Division of Electronic Engineering, Chonbuk National University

2. Electronics and Telecommunications Research Institute (ETRI)

3. Deptartment of Electronic Engineering, Wonkwang University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/14/12/14_14.20170395/_pdf

Reference10 articles.

1. [1] B. M. Baas: “A low-power, high-performance, 1024-point FFT processor,” IEEE J. Solid-State Circuits 34 (1999) 380 (DOI: 10.1109/4.748190).

2. [2] S. Y. Peng, et al.: “Energy-efficient 128∼2048/1536-point FFT processor with resource block mapping for 3 GPP-LTE system,” IEEE Int. Conf. Green Circuits Syst. (2010) 14 (DOI: 10.1109/ICGCS.2010.5543106).

3. [3] M. Khelifi, et al.: “Parallel independent FFT implementation on Intel processors and Xeon Phi for LTE and OFDM systems,” NORCAS (2015) 1 (DOI: 10.1109/NORCHIP.2015.7364402).

4. [4] S. He and M. Torkelson: “Designing pipeline FFT processor for OFDM (de)modulation,” IEEE URSI Int. Symp. Signals. Syst., Electron. (1998) 257 (DOI: 10.1109/ISSSE.1998.738077).

5. [5] J. Y. Oh and M. S. Lim: “New radix-2 to the 4th power pipeline FFT processor,” IEICE Trans. Electron. E88-C (2005) 1740 (DOI: 10.1093/ietele/e88-c.8.1740).