Design of Psub-SMPD and DNW-SMPD fabricated in a standard 0.18-µm CMOS process-Reference-Cited by-同舟云学术

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Design of Psub-SMPD and DNW-SMPD fabricated in a standard 0.18-µm CMOS process

Published:2017 Issue:14 Volume:14 Page:20170611-20170611
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Wang Rong¹,Fan Chen¹,Wang Zhi-Gong¹

Affiliation:

1. Institute of RF- & OEICs, Southeast University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/14/14/14_14.20170611/_pdf

Reference10 articles.

1. [1] T. S.-C. Kaoet al.: “A 5-Gbit/s CMOS optical receiver with integrated spatially modulated light detector and equalization,” IEEE Trans. Circuits Syst. I, Reg. Papers 57 (2010) 2844 (DOI: 10.1109/TCSI.2010.2050231).

2. [2] S.-H. Huanget al.: “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-m CMOS technology,” IEEE J. Solid-State Circuits 46 (2011) 1158 (DOI: 10.1109/JSSC.2011.2116430).

3. [3] D. Leeet al.: “An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer,” IEEE J. Solid-State Circuits 45 (2010) 2861 (DOI: 10.1109/JSSC.2010.2077050).

4. [4] M. J. Lee and W. Y. Choi: “Area-dependent photodetection frequency response characterization of silicon avalanche photodetectors fabricated with standard CMOS technology,” IEEE Trans. Electron Devices 60 (2013) 998 (DOI: 10.1109/TED.2013.2240684).

5. [5] K. Iiyamaet al.: “Silicon lateral avalanche photodiodes fabricated by standard 0.18 µm CMOS process,” IEICE Trans. Electron. E91-C (2008) 1820 (DOI: 10.1093/ietele/e91-c.11.1820).

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