DSM: A Heuristic Dynamic Spiral Mapping algorithm for network on chip-Reference-Cited by-同舟云学术

DSM: A Heuristic Dynamic Spiral Mapping algorithm for network on chip

Published:2008 Issue:13 Volume:5 Page:464-471
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Mehran Armin¹²,Khademzadeh Ahmad¹,Saeidi Samira²³

Affiliation:

1. Iran Telecom Research Center

2. CE Department, Islamic Azad University, Tehran Center Branch

3. CE Department, Islamic Azad University, Science & Research Branch

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/elex/5/13/5_13_464/_pdf

Reference8 articles.

1. [1] S. Kumar, A. Jantsch, M. Miliberg, J. Oberg, J.-P. Soininen, M. Forseli, K. Tiensyrja, and A. Hemani, “A Network on Chip Architecture and Design Methodology, ”in Proc. ISVLSI'02, Pittsburgh, USA, pp. 105-112, April 2002.

2. [2] P. Guerrier and A. Greiner, “A Generic Architecture for On-chip Packet Switched Interconnections, ”in Proc. DATE 2000, Paris, France, pp. 250-256, March 2000.

3. [3] S. Saeidi, A. Khademzadeh, and A. Mehran, “SMAP: An Intelligent Mapping Tool for Network on Chip, ”to be presented at ISSCS 2007, PID360581, Iasi, Romania, July 2007.

4. [4] Umit Y. Ogras and J. Hu, “Key Research Problems in NoC Design: A Holistic Perspective, ”in Proc CODES+ISSS'05, New Jersey, USA, pp. 69-74, Sept. 19-21, 2005.

5. [5] J. Hu and R. Marculescu, “Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints, ”in Proc. ASP-DAC'03, pp. 233-239, Jan. 2003.

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