An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA-Reference-Cited by-同舟云学术

An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA

Author:

KANAZAWA Kenji¹,MARUYAMA Tsutomu²

Affiliation:

1. Division of Information Engineering, Faculty of Engineering, Information and Systems, University of Tsukuba

2. Division of Intelligent Interaction Technologies, Faculty of Engineering, Information and Systems, University of Tsukuba

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

Reference25 articles.

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2. [2] D. McAllester, B. Selman, and H. Kautz, “Evidence for invariants in local search,” AAAI-97, pp.321-326, 1997. 10.1090/dimacs/026/25

3. [3] H.H. Hoos, “An adaptive noise mechanism for WalkSAT,” AAAI-02, pp.655-660, 2002.

5. [5] C.M. Li, W. Wei, and H. Zhang, “Combining adaptive noise and look-ahead in local search for SAT,” SAT-07, pp.121-133, 2007.

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