Protocol-Aware Packet Scheduling Algorithm for Multi-Protocol Processing in Multi-Core MPL Architecture-Reference-Cited by-同舟云学术

Protocol-Aware Packet Scheduling Algorithm for Multi-Protocol Processing in Multi-Core MPL Architecture

Published:2017 Issue:12 Volume:E100.D Page:2837-2846
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

ZHANG Runzi¹,WANG Jinlin¹,SHENG Yiqiang¹,CHEN Xiao¹,YE Xiaozhou¹

Affiliation:

1. National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E100.D/12/E100.D_2017PAP0016/_pdf

Reference28 articles.

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2. [2] K.-H. Lee, Y.-J. Lee, H. Choi, Y.D. Chung, and B. Moon, “Parallel data processing with mapreduce: a survey,” ACM SIGMOD Record, vol.40, no.4, pp.11-20, 2012. 10.1145/2094114.2094118

3. [3] Q. Zha, W. Zhang, X. Zeng, and Y. Song, “TCP/IP stack acceleration technology based on multi-core processor,” Journal of Network New Media, no.1, pp.58-64, 2013.

4. [4] Y. Shao, Y. Xue, and J. Li, “PPP: Towards parallel protocol parsing,” China Communications, vol.11, no.10, pp.106-116, 2014. 10.1109/cc.2014.6969799

5. [5] J. Kim, K. Jang, K. Lee, S. Ma, J. Shim, and S. Moon, “NBA (network balancing act): a high-performance packet processing framework for heterogeneous processors,” Proceedings of the Tenth European Conference on Computer Systems, pp.22:1-22:14, ACM, 2015. 10.1145/2741948.2741969

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