A Layout-Oriented Routing Method for Low-Latency HPC Networks-Reference-Cited by-同舟云学术

A Layout-Oriented Routing Method for Low-Latency HPC Networks

Published:2017 Issue:12 Volume:E100.D Page:2796-2807
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

KAWANO Ryuta¹,NAKAHARA Hiroshi¹,FUJIWARA Ikki²,MATSUTANI Hiroki¹,KOIBUCHI Michihiro³,AMANO Hideharu¹

Affiliation:

1. Dept. of ICS, Keio University

2. Universal Communication Research Institute, National Institute of Information and Communications Technology

3. National Institute of Informatics

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E100.D/12/E100.D_2017PAP0019/_pdf

Reference34 articles.

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4. [4] M. Koibuchi, H. Matsutani, H. Amano, D.F. Hsu, and H. Casanova, “A Case for Random Shortcut Topologies for HPC Interconnects,” Proc. of the International Symposium on Computer Architecture (ISCA), pp.177-188, June 2012. 10.1109/isca.2012.6237016

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