A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy-Reference-Cited by-同舟云学术

A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy

Published:2012 Issue:1 Volume:E95-D Page:38-45
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

YAN Chao¹,DAI Hongjun¹,CHEN Tianzhou²

Affiliation:

1. Department of Computer Science and Technology, Shandong University

2. Department of Computer Science and Technology, Zhejiang University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

http://www.jstage.jst.go.jp/article/transinf/E95.D/1/E95.D_1_38/_pdf

Reference18 articles.

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3. [3] M. Franklin, “A study of time redundant fault tolerance techniques for superscalar processors,” Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,, pp.207-215, Nov. 1995.

4. [4] A. Parashar, S. Gurumurthi, and A. Sivasubramaniam, “A complexity-effective approach to alu bandwidth enhancement for instruction-level temporal redundancy,” Proc. 31st Annual International Symposium on, Computer Architecture, pp.376-386, June 2004.

5. [5] D. Borodin and B. Juurlink, “Instruction precomputation with memoization for fault detection,” Design, Automation Test in Europe Conference Exhibition (DATE), 2010, pp.1665-1668, March 2010.