Improving Cache Partitioning Algorithms for Pseudo-LRU Policies-Reference-Cited by-同舟云学术

Improving Cache Partitioning Algorithms for Pseudo-LRU Policies

Published:2013 Issue:12 Volume:E96.D Page:2514-2523
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

ZHANG Xi¹,LIU Chuanyi¹,LIU Zhenyu²,WANG Dongsheng²

Affiliation:

1. Key Laboratory of Trustworthy Distributed Computing and Service of Ministry of Education, Beijing University of Post and Telecommunications

2. Tsinghua National Laboratory for Information Science and Technology, Tsinghua University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E96.D/12/E96.D_2514/_pdf

Reference24 articles.

1. [1] J. Chang and G.S. Sohi, “Cooperative cache partitioning for chip multiprocessors,” ICS '07, pp.242-252, 2007.

2. [2] D. Chiou, P. Jain, S. Devadas, and L. Rudolph, “Dynamic cache partitioning via columnization,” DAC '00, 2000.

3. [3] A. Jaleel, R. Cohn, C. Luk, and B. Jacob, “CMP$im: A pin-based on-the-fly multi-core cache simulator,” The Fourth Annual Workshop on Modeling, Benchmarking and Simulation (MoBS), co-located with ISCA 2008.

4. [4] A. Jaleel, W. Hasenplaugh, M. Qureshi, J. Sebot, S. Steely, Jr., and J. Emer, “Adaptive insertion policies for managing shared caches,” PACT '08, pp.208-219, 2008.

5. [5] A. Jaleel, K.B. Theobald, S.C. Steely, Jr., and J. Emer, “High performance cache replacement using re-reference interval prediction (rrip),” ISCA '10, pp.60-71, 2010.

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