Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption

Author:

HORI Yohei1,KATASHITA Toshihiro1,SAKANE Hirofumi1,TODA Kenji1,SATOH Akashi2

Affiliation:

1. Research Institute for Secure Systems (RISEC), National Institute of Advanced Industrial Science and Technology (AIST)

2. The University of Electro-Communications

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Reference42 articles.

1. [1] Y. Hori, H. Yokoyama, H. Sakane, and K. Toda, “A secure content delivery system based on a partially reconfigurable FPGA,” IEICE Trans. Inf. & Syst., vol.E91-D, no.5, pp.1398-1407, May 2008.

2. [2] C. Claus, J. Zeppenfeld, F. Muller, and W. Stechele, “Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system,” DATE'07, pp.498-503, 2007.

3. [3] J. Emmert, C. Stroud, B. Skaggs, and M. Abramovici, “Dynamic fault tolerance in FPGAs via partial reconfiguration,” FCCM 2000, pp.165-174, 2000.

4. [4] J.P. Delahaye, G. Gogniat, C. Roland, and P. Bomel, “Software radio and dynamic reconfiguration on a DSP/FPGA platform,” J. Frequenz, vol.58, no.5-6, pp.152-159, 2004.

5. [5] U.S. Department of Commerce/National Institute of Standards and Technology, “Announcing the advanced encryption standard (AES),” FIPS PUB 197, Nov. 2001.

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