An Optimization Algorithm to Build Low Congestion Multi-Ring Topology for Optical Network-on-Chip
Author:
Affiliation:
1. State Key Laboratory of Integrated Service Networks, Xidian University
2. School of Computer Science and Technology, Xidian University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software
Link
https://www.jstage.jst.go.jp/article/transinf/E101.D/7/E101.D_2017EDP7330/_pdf
Reference23 articles.
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2. [2] A.D.A. Cisse, M. Koibuchi, M. Yoshimi, H. Irie, and T. Yoshinaga, “A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation,” IEICE Trans. Inf. & Syst., vol.E96, no.12, pp.2545-2554, Dec. 2013. DOI: 10.1587/transinf.E96.D.2545 10.1587/transinf.e96.d.2545
3. [3] X. Wu, J. Xu, Y. Ye, X. Wang, M. Nikdast, Z. Wang, and Z. Wang, “An Inter/Intra-Chip Optical Network for Manycore Processors,” IEEE Transactions on Very Large Scale Integration Systems, vol.23, no.4, pp.678-691, April 2015. DOI: 10.1109/TVLSI.2014.2319089 10.1109/tvlsi.2014.2319089
4. [4] J. Jian, M. Lai, and L. Xiao, “A Fast Hierarchical Arbitration in Optical Network-on-Chip Based on Multi-Level Priority QoS,” IEICE Trans. Commun., vol.E99-B, no.4, pp.875-884, April 2016. DOI:10.1587/transcom.2015EBP3382 10.1587/transcom.2015ebp3382
5. [5] H. Gu, J. Xu, and Z. Wang, “A novel optical mesh network-on-chip for gigascale systems-on-chip,” Circuits and Systems, 2008 IEEE Asia Pacific Conference on., pp.1728-1731, Dec. 2008. DOI:10.1109/APCCAS.2008.4746373 10.1109/apccas.2008.4746373
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