A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations-Reference-Cited by-同舟云学术

A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations

Published:2010 Issue:8 Volume:E93-D Page:2040-2047
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

TAKAGI Noboru¹

Affiliation:

1. Department of Intelligent Systems Design Engineering, Toyama Prefectural University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

http://www.jstage.jst.go.jp/article/transinf/E93.D/8/E93.D_8_2040/_pdf

Reference16 articles.

1. [1] M. Goto, “Application of three-valued logic to construct the theory of relay networks,” Proc. Joint Meeting IEE, IEICE, and I. Illum. E. Japan, 1948.

2. [2] J.P. Hayes, “Digital simulation with multiple logic values,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.CAD-5, no.2, pp.274-283, 1986.

3. [3] D.W. Lewis, “Hazard detection by quinary simulation of logic devices with bounded propagation delay,” Proc. Design Automation Workshop, pp.157-164, 1972.

4. [4] S.C. Kleene, Introduction to Metamathematics, North-Holland Pub., pp.332-340, 1952.

5. [5] M. Mukaidono, “On the B-ternary logical function,” IECE Trans. Inf. & Syst., vol.55-D, no.6, pp.355-362, June 1972.

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