Single-Event-Upset Tolerant RS Flip-Flop with Small Area-Reference-Cited by-同舟云学术

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Single-Event-Upset Tolerant RS Flip-Flop with Small Area

Published:2010 Issue:12 Volume:E93-D Page:3407-3409
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

NAMBA Kazuteru¹,NAKASHIMA Kengo¹,ITO Hideo¹

Affiliation:

1. Graduate School of Advanced Integration Science, Chiba University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

http://www.jstage.jst.go.jp/article/transinf/E93.D/12/E93.D_12_3407/_pdf

Reference15 articles.

1. Characterization of soft errors caused by single event upsets in CMOS processes

2. [2] S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K.S. Kim, “Robust system design with built-in soft-error resilience,” IEEE Des. Test Comput., vol.38, no.2, pp.43-52, Feb. 2005.

3. [3] S. Krishnamohan and N.R. Mahapatra, “Analysis and design of soft-error hardened latches,” Proc. Great Lakes Symp. VLSI Des., pp.328-331, 2005.

4. Upset hardened memory design for submicron CMOS technology

5. Reliable SR latches design using local redundancy

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