The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System-Reference-Cited by-同舟云学术

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The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System

Published:2022-12-01 Issue:12 Volume:E105.D Page:2008-2018
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

SHIMIZU Tomoki¹,ITO Kohei¹,IIZUKA Kensuke¹,HIRONAKA Kazuei¹,AMANO Hideharu¹

Affiliation:

1. Dept. of Information and Computer Science, Keio University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E105.D/12/E105.D_2022PAP0009/_pdf

Reference25 articles.

1. [1] K. Hironaka, B.A. Akram, and H. Amano, “Multi-fpga management on flow-in-cloud prototype system,” 2019 20th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD), pp.443-448, 2019. 10.1109/snpd.2019.8935738

2. [2] K. Azegami, K. Musha, K. Hironaka, A.B. Ahmed, M. Koibuch, Y. Hu, and H. Amano, “A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System,” 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), pp.328-333, Oct. 2019. 10.1109/mcsoc.2019.00053

3. [3] T. Shimizu, K. Ito, K. Iizuka, K. Hironaka, and H. Amano, “Hybrid network of packet switching and stdm in a multi-fpga system,” 2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), pp.1-6, 2021. 10.1109/coolchips52128.2021.9410322

4. [4] E. Rijpkema, K.G.W. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander, “Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip,” 2003 Design, Automation and Test in Europe Conference and Exhibition, pp.350-355, March 2003. 10.1109/date.2003.1253633

5. [5] K. Goossens, J. Dielissen, and A. Radulescu, “AEthereal network on chip: concepts, architectures, and implementations,” IEEE Design Test of Computers, vol.22, no.5, pp.414-421, 2005. 10.1109/mdt.2005.99

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