Architecture of an Asynchronous FPGA for Handshake-Component-Based Design-Reference-Cited by-同舟云学术

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design

Published:2013 Issue:8 Volume:E96.D Page:1632-1644
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

KOMATSU Yoshiya¹,HARIYAMA Masanori¹,KAMEYAMA Michitaka¹

Affiliation:

1. Graduate School of Information Sciences, Tohoku University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E96.D/8/E96.D_1632/_pdf

Reference15 articles.

1. [1] K. van Berkel, J. Kessels, M. Roncken, R. Saeijs, and F. Schalij, “The VLSI-programming language Tangram and its translation into handshake circuits,” Proc. EDAC, pp.384-389, 1991.

2. [2] A. Bardsley, “Implementing Balsa Handshake Circuits,” 2000.

3. [3] Q. Zhang and G. Theodoropoulos, “Modelling SAMIPS: A synthesisable asynchronous MIPS processor,” Proc. 37th Annual Simulation Symposium, pp.205-212, 2004.

4. [4] J. Teifel and R. Manohar, “An asynchronous dataflow FPGA architecture,” IEEE Trans. Comput., vol.53, no.11, pp.1376-1392, 2004.

5. [5] R. Manohar, “Reconfigurable asynchronous logic,” Proc. IEEE Custom Integrated Circuits Conference, pp.13-20, Sept. 2006.

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