A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards-Reference-Cited by-同舟云学术

A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards

Published:2013 Issue:8 Volume:E96.D Page:1645-1653
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

NGUYEN Son-Truong¹,KONDO Masaaki¹,HIRAO Tomoya²,INOUE Koji²

Affiliation:

1. Graduate School of Information Systems, The University of Electro-Communications

2. Graduate School of Information Science and Electrical Engineering, Kyushu University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E96.D/8/E96.D_1645/_pdf

Reference21 articles.

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2. [2] N. Seki, et al., “A fine grain dynamic sleep control scheme in MIPS R3000,” IEICE Trans. Inf. & Syst.(Japanese Edition), vol.J93-D, no.6, pp.920-930, June 2010.

3. [3] I. Mogi, K. Kimura, T. Sunata, and M. Namiki, “Porting Linux OS to an evaluation board for power-saving MIPS processor “Geyser”,” IPSJ Technical Report, OS-114-9, 2010.

4. [4] K. Usami and N. Ohkubo, “A design approach for fine-grained run-time power gating using locally extracted sleep signals,” Proc. International Conference on Computer Design (ICCD), pp.155-161, 2006.

5. [5] N. McKeown, V. Anantharam, and J. Walrand, “Achieving 100% throughput in an input-queued switch,” IEEE Trans. Commun., vol.47, no.8, pp.1260-1267, 1999.

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