Effective Fixed-Point Pipelined Divider for Mobile Rendering Processors-Reference-Cited by-同舟云学术

Effective Fixed-Point Pipelined Divider for Mobile Rendering Processors

Published:2013 Issue:7 Volume:E96.D Page:1443-1448
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

PARK Yong-Jin¹,PARK Woo-Chan²,BAE Jun-Hyun¹,PARK Jinhong¹,HAN Tack-Don¹

Affiliation:

1. Department of Computer Science, Engineering College of Yonsei University

2. Department of Internet Computing, School of Computer Engineering, Sejong University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E96.D/7/E96.D_1443/_pdf

Reference12 articles.

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3. [3] A.J. Thakkar and A. Ejnioui, “Design and implementation of double precision floating point division and square root on FPGAs,” 2006 IEEE Aerospace Conf., Montana, United States, pp.1-7, March 2006.

4. [4] K. Yoshida, T. Sakamoto, and T. Hase, “A 3D graphics library for 32-bit microprocessors for embedded systems,” IEEE Trans. Consum. Electron., vol.44, no.4, pp.1107-1114, 1998.

5. [5] J.-H. Sohn, Y.-H. Park, C.-W. Yoon, R. Woo, S.-J. Park, and H.-J. Yoo, “Low-power 3D graphics processors for mobile terminals,” IEEE Commun. Mag., vol.43, no.12, pp.90-99, 2005.