1. [1] B. Agrawal and T. Sherwood, “Modeling TCAM power for next generation network devices,” IEEE ISPASS, pp.120-129, March 2006.
2. [2] S. Ahmad and R. Mahapatra, “An efficient approach to on-chip logic minimization,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.15, no.9, pp.1040-1050, Sept. 2007.
3. [3] F. Baboescu and G. Varghese, “Scalable packet classification,” IEEE/ACM Trans. Netw., vol.13, no.1, pp.2-14, Feb. 2005.
4. [4] A. Bremler-Barr and D. Hendler, “Space-efficient TCAM-based classification using gray coding,” IEEE INFOCOM, pp.1388-1396, May 2007.
5. [5] R.K. Brayton, G.D. Hachtel, C.T. McMullen, and A.L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Boston, MA, 1984.