A Power-Saving Technique for the OSGi Platform-Reference-Cited by-同舟云学术

A Power-Saving Technique for the OSGi Platform

Published:2012 Issue:5 Volume:E95.D Page:1417-1426
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

CHEN Kuo-Yi¹,LIN Chin-Yang¹,MA Tien-Yan¹,HOU Ting-Wei¹

Affiliation:

1. Department of Engineering Science, National Cheng-Kung University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E95.D/5/E95.D_5_1417/_pdf

Reference28 articles.

1. [1] O.S.G. Alliance, “OSGi service platform, core specification, Release 4, Version 4.2,” OSGi Specification, 2009.

2. [3] K. Choi, R. Soma, and M. Pedram, “Dynamic voltage and frequency scaling based on workload decomposition,” Proc. 2004 International Symposium on Low Power Electronics and Design, pp.174-179, 2004.

3. [4] K. Flautner, S. Reinhardt, and T. Mudge, “Automatic performance setting for dynamic voltage scaling,” Wireless Networks, vol.8, pp.507-520, 2002.

4. [5] R. Gonzalez and M. Horowitz, “Energy dissipation in general purpose microprocessors,” IEEE J. Solid-State Circuits, vol.31, pp.1277-1284, 2002.

5. [6] W. Kim, M.S. Gupta, G.Y. Wei, and D. Brooks, “System level analysis of fast, per-core DVFS using on-chip switching regulators,” Proc. IEEE 14th International Symposium on High Performance Computer Architecture, pp.123-134, 2008.

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