RPC: An Approach for Reducing Compulsory Misses in Packet Processing Cache-Reference-Cited by-同舟云学术

RPC: An Approach for Reducing Compulsory Misses in Packet Processing Cache

Published:2020-12-01 Issue:12 Volume:E103.D Page:2590-2599
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

YAMAKI Hayato¹,NISHI Hiroaki²,MIWA Shinobu¹,HONDA Hiroki¹

Affiliation:

1. Department of Computer and Network Engineering, The University of Electro-Communications

2. Department of System Design Engineering, Keio University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E103.D/12/E103.D_2020EDP7035/_pdf

Reference24 articles.

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3. [3] Cisco Systems, Inc., “Cisco visual networking index: Forecast and trends, 2017-2022 white paper.” http://www.cisco.com/c/en/us/solutions/collateral/service-provider/visual-net-working-index-vni/white-paper-c11-741490.html. (Accessed on 1/20/2020).

4. [4] J. Fan, C. Hu, K. He, J. Jiang, and B. Liuy, “Reducing power of traffic manager in routers via dynamic on/off-chip scheduling,” Proc. 31st Annual IEEE International Conf. Computer Communications (IEEE INFOCOM 2012), pp.1925-1933, March 2012. 10.1109/infcom.2012.6195569

5. [5] X. Zheng and X. Wang, “Comparative study of power consumption of a netfpga-based forwarding node in publish-subscribe internet routing,” Computer Communications, vol.44, pp.36-43, 2014. 10.1016/j.comcom.2014.02.015