CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis-Reference-Cited by-同舟云学术

CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis

Published:2021-12-01 Issue:12 Volume:E104.D Page:2048-2056
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

HONDA Koki¹,WEI Kaijie¹,ARAI Masatoshi²,AMANO Hideharu¹

Affiliation:

1. Dept. of Information and Computer Science, Keio University

2. Graduate School of Science and Engineering, Saitama University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E104.D/12/E104.D_2021PAP0006/_pdf

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2. [2] “Accelerate Automotive with Intel FPGAS,” 2019. https://www.intel.com/content/www/us/en/automotive/products/programmable/overview.html.

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5. [5] “Vivado Design Suite user guide high level synthesis,” 2019. https://xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug902-vivado-high-level-synthesis.pdf.

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