An FPGA Implementation for a Flexible-Length-Arithmetic Processor Employing the FDFM Processor Core Approach-Reference-Cited by-同舟云学术

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An FPGA Implementation for a Flexible-Length-Arithmetic Processor Employing the FDFM Processor Core Approach

Published:2016 Issue:12 Volume:E99.D Page:2901-2910
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

KAWAMOTO Tatsuya¹,ZHOU Xin¹,BORDIM Jacir L.²,ITO Yasuaki¹,NAKANO Koji¹

Affiliation:

1. Department of Information Engineering, Hiroshima University

2. Department of Computer Science, University of Brasilia

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E99.D/12/E99.D_2016PAP0029/_pdf

Reference23 articles.

1. [1] T. Kawamoto, Y. Ito, and K. Nakano, “A flexible-length-arithmetic processor based on FDFM approach in FPGAs,” Proc. of International Symposium on Computing and Networking, pp.364-370, 2015.

2. [2] Xilinx Inc., Virtex-6 FPGA Configuration User Guide (v3.8), 2014.

3. [3] Xilinx Inc., Virtex-6 FPGA DSP48E1 Slice User Guide (v1.3), 2011.

4. [4] Xilinx Inc., Virtex-6 FPGA Memory Resources (v1.8), 2014.

5. [5] G. Novak, “Artificial intelligence,” in Academic Press Dictionary of Science and Technology, p.160, Academic Press, San Diego, CA, 1992.

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