Reducing CPU Power Consumption with Device Utilization-Aware DVFS for Low-Latency SSDs

Author:

IMAMURA Satoshi1,YOSHIDA Eiji1,OE Kazuichi1

Affiliation:

1. Computer Systems Laboratory, Fujitsu Laboratories Ltd.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Reference32 articles.

1. [1] Intel®, “Intel® Optane™ SSD 900P Series.” https://ark.intel.com/products/123626/Intel-Optane-SSD-900P-Series-480GB-12-Height-PCIe-x4-20nm-3D-XPoint, 2017. Last accessed: Sept., 2018.

2. [2] F.T. Hady, A. Foong, B. Veal, and D. Williams, “Platform Storage Performance With 3D XPoint Technology,” Proc. IEEE, vol.105, no.9, pp.1822-1833, 2017. 10.1109/jproc.2017.2731776

3. [3] The Linux Kernel Archives, “Intel P-State driver.” https://www.kernel.org/doc/Documentation/cpu-freq/intel-pstate.txt, 2017. Last accessed: Sept., 2018.

4. [4] A. Mazouz, A. Laurent, B. Pradelle, and W. Jalby, “Evaluation of CPU Frequency Transition Latency,” Comput. Sci., vol.29, no.3-4, pp.187-195, 2014. 10.1007/s00450-013-0240-x

5. [5] R. Schöne, A Unified Infrastructure for Monitoring and Tuning the Energy Efficiency of HPC Applications, Ph.D. thesis, Technischen Universität Dresden, 2017.

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