Affiliation:
1. Institute of Microelectronics, Tsinghua University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software
Reference26 articles.
1. [1] Y. Wang, L. Liu, S. Yin, M. Zhu, P. Cao, J. Yang, and S. Wei, “On-chip memory hierarchy in one coarse-grained reconfigurable architecture to compress memory space and to reduce reconfiguration time and data-reference time,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.22, no.5, pp.983-994, 2014.
2. [2] C. Hentschel and S. Schiemenz, “Spatial up-scaler with nonlinear edge enhancement for rational factors,” International Conference on Consumer Electronics, 2007, ICCE 2007, Digest of Technical Papers, pp.1-2, 2007.
3. [3] N. Guo, L. Song, X. Yang, and W. Zhang, “Image interpolation based on decomposition,” 2010 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp.1-4, 2010.
4. [4] X. Li and M.T. Orchard, “New edge-directed interpolation,” IEEE Trans. Image Process., vol.10, no.10, pp.1521-1527, 2001.
5. [5] W. Jiang, H. Xu, G. Chen, W. Zhao, and W. Xu, “An improved edge-adaptive image scaling algorithm,” IEEE 8th International Conference on ASIC, 2009, pp.895-897, 2009.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Coarse-Grained Reconfigurable Array Architectures;Handbook of Signal Processing Systems;2018-10-14