Battery-Aware Loop Nests Mapping for CGRAs

Author:

PENG Yu1,YIN Shouyi1,LIU Leibo1,WEI Shaojun1

Affiliation:

1. Institute of Microelectronics, Tsinghua University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Reference17 articles.

1. [1] Q. Wu, M. Pedram, and X. Wu, “Clock-gating and its application to low power design of sequential circuits,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol.47, no.3, pp.415-420, 2000.

2. [2] Z. Hu, A. Buyuktosunoglu, V. Srinivasan, V. Zyuban, H. Jacobson, and P. Bose, “Microarchitectural techniques for power gating of execution units,” Proc. 2004 International Symposium on Low Power Electronics and Design, pp.32-37, 2004.

3. [3] M. Zhu, L. Liu, S. Yin, Y. Wang, W. Wang, and S. Wei, “A reconfigurable multi-processor SoC for media applications,” Proc. 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pp.2011-2014, 2010.

4. [4] D. Rakhmatov and S. Vrudhula, “Energy management for battery-powered embedded systems,” ACM Trans. Embedded Computing Systems (TECS), vol.2, no.3, pp.277-324, 2003.

5. [5] M. Hamzeh, A. Shrivastava, and S. Vrudhula, “Epimap: Using epimorphism to map applications on CGRAs,” Proc. 49th Annual Design Automation Conference, pp.1284-1291, 2012.

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1. Coarse-Grained Reconfigurable Array Architectures;Handbook of Signal Processing Systems;2018-10-14

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