Affiliation:
1. Faculty of Science and Technology, Keio University
2. National Institute of Informatics
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software
Reference18 articles.
1. [1] W.J. Dally and B. Towles, “Route packets, not wires: On-chip interconnection networks, ” Proc. 38th Design Automation Conference, pp.684-689, June 2001.
2. [2] T. Marescaux, A. Bartic, D. Verkest, S. Vernalde, and R. Lauwereins, “Interconnection networks enable fine-grain dynamic multi-tasking on FPGAs, ” Proc. Field-Programmable Logic and Applications (FPL), pp.795-805, Sept. 2002.
3. [3] M.P. Vestias and H.C. Neto, “Router design for application specific networks-on-chip on reconfigurable systems, ” Proc. Field-Programmable Logic and Applications (FPL), pp.389-394, Aug. 2007.
4. [4] D. Wang, H. Matsutani, M. Koibuchi, and H. Amano, “A temporal correlation based port combination methodology for networks-on-chip on reconfigurable systems, ” Proc. Field-Programmable Logic and Applications (FPL), pp.383-388, Aug. 2007.
5. [5] M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge, and R.B. Brown, “Mibench: A free, commercially representative embedded benchmark suite, ” Proc. IEEE International Workshop on Workload Characterization (WWC), pp.3-14, 2001.