Low-Cost Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip
Author:
Affiliation:
1. State Key Laboratory of Wide Bandgap Semiconductor Technology Disciplines, Xidian University
2. Institute of Natural Resources Environment and Historical Culture, Xian Yang Normal University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software
Link
https://www.jstage.jst.go.jp/article/transinf/E100.D/4/E100.D_2016EDL8208/_pdf
Reference8 articles.
1. [1] M. Valinataja, S. Mohammadi, J. Plosila, P. Liljeberg, and H. Tenhunen, “A reconfigurable and adaptive routing method for fault-tolerant mesh based networks-on-chip,” Int. J. Electronics and Communications (AEU), vol.65, no.7, pp.630-640, 2011.
2. [2] R. Xie, J. Cai, and X. Xin, “Simple fault-tolerant method to balance load in network-on-chip,” Electronics Letters, vol.52, no.10, pp.814-816, 2016.
3. [3] M. Ebrahimi and M. Daneshtalab, “A light-weight fault-tolerant routing method tolerating faulty links and routers,” Computing, vol.97, no.6, pp.631-648, 2015.
4. [4] M. Ebrahimi, M. Daneshtalab, and J. Plosila, “High Performance Fault-Tolerant Routing Algorithm for NoC-based Many-Core Systems,” 2013 21st Euromicro International Conference on Parallel, Distributed and Network-Based Processing, pp.462-469, 2013.
5. [5] F. Chaix, D. Avresky, N.-E. Zergainoh, and M. Nicolaidis, “A fault-tolerant deadlock-free adaptive routing for On Chip interconnects,” Design Automation & Test in Europe, pp.1-4, 2011.
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