An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation
Author:
Affiliation:
1. department of Creative Engineering, National Institute of Technology, Tsuruoka College
2. Electronics Engineering Department, King Monkut's Institute of Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software
Link
https://www.jstage.jst.go.jp/article/transinf/E100.D/12/E100.D_2017EDP7039/_pdf
Reference19 articles.
1. [1] R.E. Blahut, “A universal reed-solomon decoder,” IBM Journal of Research and Development, vol.28, no.2, pp.150-158, March 1984. 10.1147/rd.282.0150
2. [2] S. Choomchuay and B. Arambepola, “Time domain algorithms and architechures for reed-solomn decoding,” IEE Proceedings-I, vol.140, no.3, pp.150-158, June 1984. 10.1049/ip-i-2.1993.0029
3. [3] R. Koetter and A. Vardy, “Algebraic soft-decision decoding of reed-solomon codes,” IEEE Trans. Inf. Theory, vol.49, no.11, pp.2809-2825, Nov. 2003. 10.1109/tit.2003.819332
4. [4] J.S. Yedidia, W.T. Freeman, and Y. Weiss, “Constructing free-energy approximations and generalized belief propagation algorithms,” IEEE Transactions on Information Theory, vol.51, no.7, pp.2282-2312, 2005. 10.1109/tit.2005.850085
5. [5] J. Jiang and K.R. Narayanan, “Iterative soft decoding of reed solomon codes,” IEEE Commun. Lett., vol.8, no.4, pp.244-246, May 2004. 10.1109/lcomm.2004.827977
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