Energy- and Traffic-Balance-Aware Mapping Algorithm for Network-on-Chip-Reference-Cited by-同舟云学术

Energy- and Traffic-Balance-Aware Mapping Algorithm for Network-on-Chip

Published:2013 Issue:3 Volume:E96.D Page:719-722
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

DENG Zhi¹,GU Huaxi¹,YANG Yingtang²,YOU Hua³

Affiliation:

1. State Key Laboratory of Integrated Service Networks, Xidian University

2. School of Microelectronic, Xidian University

3. Intel Asia-Pacific Research and development Ltd

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E96.D/3/E96.D_719/_pdf

Reference10 articles.

1. [1] J. Hu and R. Marculescu, “Energy-aware mapping for tile-based NoC architectures under performance constraints,” Proc. Asia and South Pacific Design Automation Conference, Kitakyushu, Japan, Jan. 2003.

2. [2] L. Tang and S. Kumar, “A two-step genetic algorithm for mapping task graphs to a network on chip architecture,” Proc. Euromicro Symposium on Digital System Design, Turkey, Sept. 2003.

3. [3] A.A. Morgan, H. Elmiligi, M.W. El-Kharashi, and F. Gebali, “Multi-objective optimization for networks-on-chip architectures using genetic algorithms,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, May 2010.

4. [4] B. Fu, Y. Han, H. Li, and X.w. Li, “A new multiple-round dimension-order routing for networks-on-chip,” IEICE Trans. Inf. & Syst., vol.E94-D, no.4, pp.809-821, April 2011.

5. [5] J. Sepulveda, M. Strum, W.J. Chau, and G. Guy, “A multi-objective approach for multi-application NoC mapping,” Proc. IEEE Second Latin American Symposium on Circuits and Systems (LASCAS), Bogota, Colombia, Feb. 2011.

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