Reuse distance-based shared LLC management mechanism for heterogeneous CPU-GPU systems
Author:
Affiliation:
1. Graduate School of Information Sciences, Tohoku University
2. School of Engineering, Tokyo Denki University
3. Cyberscience Center, Tohoku University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Link
https://www.jstage.jst.go.jp/article/elex/21/4/21_21.20230520/_pdf
Reference30 articles.
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3. [3] T. Burd, et al.: “Zen3: The amd 2nd generation 7nm x86-64 microprocessor core,” IEEE ISSCC 65 IEEE (2022) 1 (DOI: 10.1109/HCS55958.2022.9895609).
4. [4] V. Garcıa, et al.: “Evaluating the effect of last-level cache sharing on integrated gpu-cpu systems with heterogeneous applications,” IEEE IISWC (2016) 1 (DOI: 10.1109/iiswc.2016.7581277).
5. [5] J. Lee, et al.: “TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture,” IEEE HPCA (2012) 1 (DOI: 10.1109/hpca.2012.6168947).
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