Design and implementation of IDELAY-RO PUF in Xilinx ZYNQ PSoCs-Reference-Cited by-同舟云学术

Design and implementation of IDELAY-RO PUF in Xilinx ZYNQ PSoCs

Published:2024-03-25 Issue:6 Volume:21 Page:20240013-20240013
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Mao Zhen¹²,Li Bing¹,Peng Linning¹,Li Yuanzhong²

Affiliation:

1. School of Cyber Science and Engineering, Southeast University

2. China Electronics Technology Group Corporation No.58 Research Institute

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Link

https://www.jstage.jst.go.jp/article/elex/21/6/21_21.20240013/_pdf

Reference32 articles.

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2. [2] M. Ender, et al.: “The unpatchable silicon: a full break of the bitstream encryption of Xilinx 7-series FPGAs,” (2021) (DOI: 10.48550/arXiv.2105.13756).

3. [3] N.N. Anandakumar, et al.: “FPGA-based physical unclonable functions: a comprehensive overview of theory and architectures,” Integration 81 (2021) 175 (DOI: 10.1016/j.vlsi.2021.06.001).

4. [4] J.W. Lee, et al.: “A technique to build a secret key in integrated circuits for identification and authentication applications,” Dig. Tech. Papers (2004) 176 (DOI: 10.1109/VLSIC.2004.1344203).

5. [5] D.P. Sahoo, et al.: “A multiplexer-based arbiter PUF composition with enhanced reliability and security,” IEEE Trans. Comput. 67 (2018) 403 (DOI: 10.1109/TC.2017.2749226).

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