Investigation of heat dissipation structure embedded in substrate of power chip based on grid-type thermal through silicon vias
Author:
Affiliation:
1. Dept. of Electronics, Guizhou University
2. Semiconductor Power Device Reliability Engineering Research Center of Ministry of Education
3. Guizhou Provincial Key Lab for Micro-Nano-Electronics and Software
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Link
https://www.jstage.jst.go.jp/article/elex/21/11/21_21.20240185/_pdf
Reference30 articles.
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2. [2] K. Shenai: “Power semiconductor devices: design and manufacturing for improved field reliability (invited),” Proc. Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (2002) P024 (DOI: 10.1109/iccdcs.2002.1004104).
3. [3] A. Mosayyebzadeh, et al.: “Thermal and power aware task mapping on 3D network on chip,” Computers & Electrical Engineering 51 (2016) 157 (DOI: 10.1016/j.compeleceng.2015.12.001).
4. [4] A.V. Efanov, et al.: “Manufacturing quality control systems of power semiconductor devices and informative parameters of their reliability,” Russian Electrical Engineering 90 (2019) 212 (DOI: 10.3103/s1068371219030076).
5. [5] H. Ren, et al.: “High-reliability wireless packaging for high-temperature SiC power device sintered by novel organic-free nanomaterial,” IEEE Trans. Compon. Packag. Manuf. Technol. 10 (2020) 1953 (DOI: 10.1109/tcpmt.2020.3038430).
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