Structural analysis attack on asynchronous obfuscated circuits
Author:
Affiliation:
1. Institute of VLSI Design, Zhejiang University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Link
https://www.jstage.jst.go.jp/article/elex/21/11/21_21.20240107/_pdf
Reference30 articles.
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3. [3] B.K. Natarajan and V. Senniappan: “Logic obfuscation technique using configurable gate diffusion input for improved hardware security,” IEICE Electron. Express 15 (2018) 20180802 (DOI: 10.1587/elex.15.20180802).
4. [4] A.E. Caldwell, et al.: “Effective iteractive techniques for fingerprinting design IP,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 23 (2004) 208 (DOI: 10.1109/tcad.2003.822126).
5. [5] A. Chakraborty, et al.: “Keynote: a disquisition on logic locking,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 39 (2020) 1952 (DOI: 10.1109/tcad.2019.2944586).
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