Stacked-FET linear SOI CMOS SPDT antenna switch with input P1dB greater than 40dBm
Author:
Affiliation:
1. Department of EE, Korea Advanced Institute of Science and Technology (KAIST)
2. National NanoFab Center (NNFC)
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/9/24/9_1813/_pdf
Reference1 articles.
1. [4] D. Im, et al., “DC SOI MOSFET characterization and optimization method for rapid evaluation of RF switch power handling capability,” Proc. EuroSOI Workshop, pp. 105-106, Jan. 2012.
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