An ultra-long FFT architecture implemented in a reconfigurable application specified processor
Author:
Affiliation:
1. School of Electronic Science and Engineering, Nanjing University
2. Nanjing Research Institute of Electronic Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/13/13/13_13.20160504/_pdf
Reference17 articles.
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2. [2] E. Cetin, et al.: “An integrated 256-point complex FFT processor for real-time spectrum analysis and measurement,” IEEE Instrumentation and Measurement Technology Conference, 1997. IMTC/97. Proc. Sensing, Processing, Networking (1997) 96 (DOI: 10.1109/IMTC.1997.603923).
3. [3] M. Sang-Chul, et al.: “Area-efficient memory-based architecture for FFT processing,” Proc. of the 2003 International Symposium on Circuits and Systems. ISCAS ’03 (2003) V (DOI: 10.1109/ISCAS.2003.1206198).
4. [4] M. Zhen-Guoet al.: “A novel memory-based FFT architecture for real-valued signals based on a radix-2 decimation-in-frequency algorithm,” IEEE Trans. Circuits Syst. II, Exp. Briefs 62 (2015) 876 (DOI: 10.1109/TCSII.2015.2435522).
5. [5] K.-H. Chen: “A low-memory-access length-adaptive architecture for 2n-point FFT,” Circuits Syst. Signal Process. 34 (2015) 459 (DOI: 10.1007/s00034-014-9862-x).
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