Floating-point operation based reconfigurable architecture for radar processing
Author:
Affiliation:
1. School of Electronic Science and Engineering, Nanjing University
2. Nanjing Research Institute of Electronics Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/13/21/13_13.20160893/_pdf
Reference15 articles.
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2. [2] Y. Kimet al.: “Design space exploration for efficient resource utilization in coarse-grained reconfigurable architecture,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18 (2010) 1471 (DOI: 10.1109/TVLSI.2009.2025280).
3. [3] Y. Kim, et al.: in Handbook of Signal Processing Systems (Springer, 2013) 553.
4. [4] M. Stojilovicet al.: “Selective flexibility: creating domain-specific reconfigurable arrays,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32 (2013) 681 (DOI: 10.1109/TCAD.2012.2235127).
5. [5] D. Novo, et al.: “Mapping a multiple antenna SDM-OFDM receiver on the ADRES coarse-grained reconfigurable processor,” IEEE Workshop on Signal Processing Systems Design and Implementation (2005) 473 (DOI: 10.1109/SIPS.2005.1579915).
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