A low-jitter BMCDR for half-rate PON systems
Author:
Affiliation:
1. School of Electrical and Electronics Engineering, Chung-Ang University
2. Device Solution Division, Samsung Electronics
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/14/1/14_13.20161045/_pdf
Reference10 articles.
1. [1] S. Gierkink: “A 2.5 Gb/s run-length-tolerant burst-mode CDR based on a 1/8th-rate dual pulse ring oscillator,” IEEE J. Solid-State Circuits 43 (2008) 1763 (DOI: 10.1109/JSSC.2008.926736).
2. [2] R. Yuet al.: “10-Gb/s BM-CDR circuit with synchronous data output for optical networks,” IEEE Photonics Technol. Lett. 25 (2013) 508 (DOI: 10.1109/LPT.2013.2242461).
3. [3] J.-H. Junget al.: “A 2.5 Gb/s burst-mode clock and data recovery with digital frequency calibration and jitter rejection scheme,” IEIE J. Inst. Electron. Inf. Eng. 50 (2013) 87 (DOI: 10.5573/ieek.2013.50.7.087).
4. [4] H. Katsuraiet al.: “An injection-controlled 10-Gb/s burst-mode CDR circuit for a 1 G/10 G PON system,” IEICE Trans. Electron. E94-C (2011) 582 (DOI: 10.1587/transele.E94.C.582).
5. [5] J.-I. Kaniet al.: “Next-generation PON-part 1: Technology roadmap and general requirements,” IEEE Commun. Mag. 47 (2009) 43 (DOI: 10.1109/MCOM.2009.5307465).
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