Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters-Reference-Cited by-同舟云学术

Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters

Published:2014 Issue:4 Volume:E97.C Page:360-368
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

MIYAMORI Takashi¹,XU Hui¹,USUI Hiroyuki¹,HOSODA Soichiro¹,SANO Toru¹,YAMAMOTO Kazumasa¹,KODAKA Takeshi¹,NONOGAKI Nobuhiro¹,OZAKI Nau¹,TANABE Jun¹

Affiliation:

1. Toshiba Corporation Semiconductor & Storage Products Company

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E97.C/4/E97.C_360/_pdf

Reference13 articles.

1. [1] J. Howard, S. Dighe, S.R. Vangal, G. Ruhl, N. Borkar, S. Jain, V. Erraguntla, M. Konow, M. Riepen, M. Gries, G. Droege, T. Lund-Larsen, S. Steibl, S. Borkar, V.K. De, and R. Van Der Wijngaart, “A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS,” ISSCC, pp.108-109, 2010.

2. [2] S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, P. Iyer, A. Singh, T. Jacob, S. Jain, S. Venkataraman, Y. Hoskote, and N. Borkar, “An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS,” ISSCC, pp.98-99, 2007.

3. [3] H. Xu, J. Tanabe, H. Usui, S. Hosoda, T. Sano, K. Yamamoto, T. Kodaka, N. Nonogaki, N. Ozaki, and T. Miyamori, “A Low Power Many-Core SoC with Two 32-Core Clusters Connected by Tree based NoC for Multimedia Applications,” Symposium on VLSI Circuits, pp.150-151, 2012.

4. [4] S. Nomura, F. Tachibana, T. Fujita, C.K. Teh, H. Usui, F. Yamane, Y. Miyamoto, K. Chaiyasit, H. Hara, T. Yamashita, J. Tanabe, M. Uchiyama, Y. Tsuboi, T. Miyamori, T. Kitahara, H. Sato, Y. Homma, S. Matsumoto, K. Seki, Y. Watanabe, M. Hamada, and M. Takahashi, “A 9.7mW AAC-decoding, 620mW H.264 720p 60fps decoding, 8-core media processor with embedded forward-body-biasing and power-gating circuit in 65nm CMOS technology,” ISSCC, pp.262-263, 2008.

5. [5] T. Mori, Y. Ueda, N. Nonogaki, T. Terazawa, M. Sroka, T. Fujita, T. Kodaka, T. Mori, K. Morita, H. Arakida, T. Miura, Y. Okuda, T. Kizu, and Y. Tsuboi, “A power, performance scalable eight-cores media processor for mobile multimedia applications,” JSSCC, pp.2957-2965, 2009.